Here are specific details on what constraint letters you can use with
asm operands.
Constraints can say whether
an operand may be in a register, and which kinds of register; whether the
operand can be a memory reference, and which kinds of address; whether the
operand may be an immediate constant, and which possible values it may
have. Constraints can also require two operands to match.
6.36.1. Simple Constraints
The simplest kind of constraint is a string full of letters, each of
which describes one kind of operand that is permitted. Here are
the letters that are allowed:
whitespace
Whitespace characters are ignored and can be inserted at any position
except the first. This enables each alternative for different operands to
be visually aligned in the machine description even if they have different
number of constraints and modifiers.
m
A memory operand is allowed, with any kind of address that the machine
supports in general.
o
A memory operand is allowed, but only if the address is
offsettable. This means that adding a small integer (actually,
the width in bytes of the operand, as determined by its machine mode)
may be added to the address and the result is also a valid memory
address.
For example, an address which is constant is offsettable; so is an
address that is the sum of a register and a constant (as long as a
slightly larger constant is also within the range of address-offsets
supported by the machine); but an autoincrement or autodecrement
address is not offsettable. More complicated indirect/indexed
addresses may or may not be offsettable depending on the other
addressing modes that the machine supports.
Note that in an output operand which can be matched by another
operand, the constraint letter o is valid only when accompanied
by both < (if the target machine has predecrement addressing)
and > (if the target machine has preincrement addressing).
V
A memory operand that is not offsettable. In other words, anything that
would fit the m constraint but not the o constraint.
<
A memory operand with autodecrement addressing (either predecrement or
postdecrement) is allowed.
>
A memory operand with autoincrement addressing (either preincrement or
postincrement) is allowed.
r
A register operand is allowed provided that it is in a general
register.
i
An immediate integer operand (one with constant value) is allowed.
This includes symbolic constants whose values will be known only at
assembly time.
n
An immediate integer operand with a known numeric value is allowed.
Many systems cannot support assembly-time constants for operands less
than a word wide. Constraints for these operands should use n
rather than i.
I, J, K, … P
Other letters in the range I through P may be defined in
a machine-dependent fashion to permit immediate integer operands with
explicit integer values in specified ranges. For example, on the
68000, I is defined to stand for the range of values 1 to 8.
This is the range permitted as a shift count in the shift
instructions.
E
An immediate floating operand (expression code const_double) is
allowed, but only if the target floating point format is the same as
that of the host machine (on which the compiler is running).
F
An immediate floating operand (expression code const_double or
const_vector) is allowed.
G, H
G and H may be defined in a machine-dependent fashion to
permit immediate floating operands in particular ranges of values.
s
An immediate integer operand whose value is not an explicit integer is
allowed.
This might appear strange; if an insn allows a constant operand with a
value not known at compile time, it certainly must allow any known
value. So why use s instead of i? Sometimes it allows
better code to be generated.
For example, on the 68000 in a fullword instruction it is possible to
use an immediate operand; but if the immediate value is between −128
and 127, better code results from loading the value into a register and
using the register. This is because the load into the register can be
done with a moveq instruction. We arrange for this to happen
by defining the letter K to mean "any integer outside the
range −128 to 127", and then specifying Ks in the operand
constraints.
g
Any register, memory or immediate integer operand is allowed, except for
registers that are not general registers.
X
Any operand whatsoever is allowed.
0, 1, 2, … 9
An operand that matches the specified operand number is allowed. If a
digit is used together with letters within the same alternative, the
digit should come last.
This number is allowed to be more than a single digit. If multiple
digits are encountered consecutively, they are interpreted as a single
decimal integer. There is scant chance for ambiguity, since to-date
it has never been desirable that 10 be interpreted as matching
either operand 1 or operand 0. Should this be desired, one
can use multiple alternatives instead.
This is called a matching constraint and what it really means is
that the assembler has only a single operand that fills two roles
which asm distinguishes. For example, an add instruction uses
two input operands and an output operand, but on most CISC
machines an add instruction really has only two operands, one of them an
input-output operand:
addl #35,r12
Matching constraints are used in these circumstances.
More precisely, the two operands that match must include one input-only
operand and one output-only operand. Moreover, the digit must be a
smaller number than the number of the operand that uses it in the
constraint.
p
An operand that is a valid memory address is allowed. This is
for "load address" and "push address" instructions.
p in the constraint must be accompanied by address_operand
as the predicate in the match_operand. This predicate interprets
the mode specified in the match_operand as the mode of the memory
reference for which the address would be valid.
other-letters
Other letters can be defined in machine-dependent fashion to stand for
particular classes of registers or other arbitrary operand types.
d, a and f are defined on the 68000/68020 to stand
for data, address and floating point registers.
6.36.2. Multiple Alternative Constraints
Sometimes a single instruction has multiple alternative sets of possible
operands. For example, on the 68000, a logical-or instruction can combine
register or an immediate value into memory, or it can combine any kind of
operand into a register; but it cannot combine one memory location into
another.
These constraints are represented as multiple alternatives. An alternative
can be described by a series of letters for each operand. The overall
constraint for an operand is made from the letters for this operand
from the first alternative, a comma, the letters for this operand from
the second alternative, a comma, and so on until the last alternative.
If all the operands fit any one alternative, the instruction is valid.
Otherwise, for each alternative, the compiler counts how many instructions
must be added to copy the operands so that that alternative applies.
The alternative requiring the least copying is chosen. If two alternatives
need the same amount of copying, the one that comes first is chosen.
These choices can be altered with the ? and ! characters:
?
Disparage slightly the alternative that the ? appears in,
as a choice when no alternative applies exactly. The compiler regards
this alternative as one unit more costly for each ? that appears
in it.
!
Disparage severely the alternative that the ! appears in.
This alternative can still be used if it fits without reloading,
but if reloading is needed, some other alternative will be used.
6.36.3. Constraint Modifier Characters
Here are constraint modifier characters.
=
Means that this operand is write-only for this instruction: the previous
value is discarded and replaced by output data.
+
Means that this operand is both read and written by the instruction.
When the compiler fixes up the operands to satisfy the constraints,
it needs to know which operands are inputs to the instruction and
which are outputs from it. = identifies an output; +
identifies an operand that is both input and output; all other operands
are assumed to be input only.
If you specify = or + in a constraint, you put it in the
first character of the constraint string.
&
Means (in a particular alternative) that this operand is an
earlyclobber operand, which is modified before the instruction is
finished using the input operands. Therefore, this operand may not lie
in a register that is used as an input operand or as part of any memory
address.
& applies only to the alternative in which it is written. In
constraints with multiple alternatives, sometimes one alternative
requires & while others do not. See, for example, the
movdf insn of the 68000.
An input operand can be tied to an earlyclobber operand if its only
use as an input occurs before the early result is written. Adding
alternatives of this form often allows GCC to produce better code
when only some of the inputs can be affected by the earlyclobber.
See, for example, the mulsi3 insn of the ARM.
& does not obviate the need to write =.
%
Declares the instruction to be commutative for this operand and the
following operand. This means that the compiler may interchange the
two operands if that is the cheapest way to make all operands fit the
constraints.
GCC can only handle one commutative pair in an asm; if you use more,
the compiler may fail. Note that you need not use the modifier if
the two alternatives are strictly identical; this would only waste
time in the reload pass.
#
Says that all following characters, up to the next comma, are to be
ignored as a constraint. They are significant only for choosing
register preferences.
*
Says that the following character should be ignored when choosing
register preferences. * has no effect on the meaning of the
constraint as a constraint, and no effect on reloading.
6.36.4. Constraints for Particular Machines
Whenever possible, you should use the general-purpose constraint letters
in asm arguments, since they will convey meaning more readily to
people reading your code. Failing that, use the constraint letters
that usually have very similar meanings across architectures. The most
commonly used constraints are m and r (for memory and
general-purpose registers respectively; Section 6.36.1 Simple Constraints), and
I, usually the letter indicating the most common
immediate-constant format.
For each machine architecture, the
config/machine/machine.h file defines additional
constraints. These constraints are used by the compiler itself for
instruction generation, as well as for asm statements; therefore,
some of the constraints are not particularly interesting for asm.
The constraints are defined through these macros:
REG_CLASS_FROM_LETTER
Register class constraints (usually lowercase).
CONST_OK_FOR_LETTER_P
Immediate constant constraints, for non-floating point constants of
word size or smaller precision (usually uppercase).
CONST_DOUBLE_OK_FOR_LETTER_P
Immediate constant constraints, for all floating point constants and for
constants of greater than word size precision (usually uppercase).
EXTRA_CONSTRAINT
Special cases of registers or memory. This macro is not required, and
is only defined for some machines.
Inspecting these macro definitions in the compiler source for your
machine is the best way to be certain you have the right constraints.
However, here is a summary of the machine-dependent constraints
available on some particular machines.
ARM family--arm.h
f
Floating-point register
F
One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
or 10.0
G
Floating-point constant that would satisfy the constraint F if it
were negated
I
Integer that is valid as an immediate operand in a data processing
instruction. That is, an integer in the range 0 to 255 rotated by a
multiple of 2
J
Integer in the range −4095 to 4095
K
Integer that satisfies constraint I when inverted (ones complement)
L
Integer that satisfies constraint I when negated (twos complement)
M
Integer in the range 0 to 32
Q
A memory reference where the exact address is in a single register
(`m' is preferable for asm statements)
R
An item in the constant pool
S
A symbol in the text segment of the current file
AVR family--avr.h
l
Registers from r0 to r15
a
Registers from r16 to r23
d
Registers from r16 to r31
w
Registers from r24 to r31. These registers can be used in adiw command
e
Pointer register (r26-r31)
b
Base pointer register (r28-r31)
q
Stack pointer register (SPH:SPL)
t
Temporary register r0
x
Register pair X (r27:r26)
y
Register pair Y (r29:r28)
z
Register pair Z (r31:r30)
I
Constant greater than −1, less than 64
J
Constant greater than −64, less than 1
K
Constant integer 2
L
Constant integer 0
M
Constant that fits in 8 bits
N
Constant integer −1
O
Constant integer 8, 16, or 24
P
Constant integer 1
G
A floating point constant 0.0
PowerPC and IBM RS6000--rs6000.h
b
Address base register
f
Floating point register
v
Vector register
h
MQ, CTR, or LINK register
q
MQ register
c
CTR register
l
LINK register
x
CR register (condition register) number 0
y
CR register (condition register)
z
FPMEM stack memory for FPR-GPR transfers
I
Signed 16-bit constant
J
Unsigned 16-bit constant shifted left 16 bits (use L instead for
SImode constants)
K
Unsigned 16-bit constant
L
Signed 16-bit constant shifted left 16 bits
M
Constant larger than 31
N
Exact power of 2
O
Zero
P
Constant whose negation is a signed 16-bit constant
G
Floating point constant that can be loaded into a register with one
instruction per word
Q
Memory operand that is an offset from a register (m is preferable
for asm statements)
R
AIX TOC entry
S
Constant suitable as a 64-bit mask operand
T
Constant suitable as a 32-bit mask operand
U
System V Release 4 small data area reference
Intel 386--i386.h
q
a, b, c, or d register for the i386.
For x86-64 it is equivalent to r class. (for 8-bit instructions that
do not use upper halves)
Q
a, b, c, or d register. (for 8-bit instructions,
that do use upper halves)
R
Legacy register--equivalent to r class in i386 mode.
(for non-8-bit registers used together with 8-bit upper halves in a single
instruction)
A
Specifies the a or d registers. This is primarily useful
for 64-bit integer values (when in 32-bit mode) intended to be returned
with the d register holding the most significant bits and the
a register holding the least significant bits.
f
Floating point register
t
First (top of stack) floating point register
u
Second floating point register
a
a register
b
b register
c
c register
C
Specifies constant that can be easily constructed in SSE register without
loading it from memory.
d
d register
D
di register
S
si register
x
xmm SSE register
y
MMX register
I
Constant in range 0 to 31 (for 32-bit shifts)
J
Constant in range 0 to 63 (for 64-bit shifts)
K
0xff
L
0xffff
M
0, 1, 2, or 3 (shifts for lea instruction)
N
Constant in range 0 to 255 (for out instruction)
Z
Constant in range 0 to 0xffffffff or symbolic reference known to fit specified range.
(for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
e
Constant in range −2147483648 to 2147483647 or symbolic reference known to fit specified range.
(for using immediates in 64-bit x86-64 instructions)
G
Standard 80387 floating point constant
Intel 960--i960.h
f
Floating point register (fp0 to fp3)
l
Local register (r0 to r15)
b
Global register (g0 to g15)
d
Any local or global register
I
Integers from 0 to 31
J
0
K
Integers from −31 to 0
G
Floating point 0
H
Floating point 1
Intel IA-64--ia64.h
a
General register r0 to r3 for addl instruction
b
Branch register
c
Predicate register (c as in "conditional")
d
Application register residing in M-unit
e
Application register residing in I-unit
f
Floating-point register
m
Memory operand.
Remember that m allows postincrement and postdecrement which
require printing with %Pn on IA-64.
Use S to disallow postincrement and postdecrement.
G
Floating-point constant 0.0 or 1.0
I
14-bit signed integer constant
J
22-bit signed integer constant
K
8-bit signed integer constant for logical instructions
L
8-bit adjusted signed integer constant for compare pseudo-ops
M
6-bit unsigned integer constant for shift counts
N
9-bit signed integer constant for load and store postincrements
O
The constant zero
P
0 or -1 for dep instruction
Q
Non-volatile memory for floating-point loads and stores
R
Integer constant in the range 1 to 4 for shladd instruction
S
Memory operand except postincrement and postdecrement
IP2K--ip2k.h
a
DP or IP registers (general address)
f
IP register
j
IPL register
k
IPH register
b
DP register
y
DPH register
z
DPL register
q
SP register
c
DP or SP registers (offsettable address)
d
Non-pointer registers (not SP, DP, IP)
u
Non-SP registers (everything except SP)
R
Indirect through IP - Avoid this except for QImode, since we
can't access extra bytes
S
Indirect through SP or DP with short displacement (0..127)
T
Data-section immediate value
I
Integers from −255 to −1
J
Integers from 0 to 7--valid bit number in a register
K
Integers from 0 to 127--valid displacement for addressing mode
L
Integers from 1 to 127
M
Integer −1
N
Integer 1
O
Zero
P
Integers from 0 to 255
MIPS--mips.h
d
General-purpose integer register
f
Floating-point register (if available)
h
Hi register
l
Lo register
x
Hi or Lo register
y
General-purpose integer register
z
Floating-point status register
I
Signed 16-bit constant (for arithmetic instructions)
Constant with low 16 bits zero (can be loaded with lui)
M
32-bit constant which requires two instructions to load (a constant
which is not I, K, or L)
N
Negative 16-bit constant
O
Exact power of two
P
Positive 16-bit constant
G
Floating point zero
Q
Memory reference that can be loaded with more than one instruction
(m is preferable for asm statements)
R
Memory reference that can be loaded with one instruction
(m is preferable for asm statements)
S
Memory reference in external OSF/rose PIC format
(m is preferable for asm statements)
Motorola 680x0--m68k.h
a
Address register
d
Data register
f
68881 floating-point register, if available
I
Integer in the range 1 to 8
J
16-bit signed number
K
Signed number whose magnitude is greater than 0x80
L
Integer in the range −8 to −1
M
Signed number whose magnitude is greater than 0x100
G
Floating point constant that is not a 68881 constant
Motorola 68HC11 & 68HC12 families--m68hc11.h
a
Register 'a'
b
Register 'b'
d
Register 'd'
q
An 8-bit register
t
Temporary soft register _.tmp
u
A soft register _.d1 to _.d31
w
Stack pointer register
x
Register 'x'
y
Register 'y'
z
Pseudo register 'z' (replaced by 'x' or 'y' at the end)
A
An address register: x, y or z
B
An address register: x or y
D
Register pair (x:d) to form a 32-bit value
L
Constants in the range −65536 to 65535
M
Constants whose 16-bit low part is zero
N
Constant integer 1 or −1
O
Constant integer 16
P
Constants in the range −8 to 2
SPARC--sparc.h
f
Floating-point register on the SPARC-V8 architecture and
lower floating-point register on the SPARC-V9 architecture.
e
Floating-point register. It is equivalent to f on the
SPARC-V8 architecture and contains both lower and upper
floating-point registers on the SPARC-V9 architecture.
c
Floating-point condition code register.
d
Lower floating-point register. It is only valid on the SPARC-V9
architecture when the Visual Instruction Set is available.
b
Floating-point register. It is only valid on the SPARC-V9 architecture
when the Visual Instruction Set is available.
h
64-bit global or out register for the SPARC-V8+ architecture.
I
Signed 13-bit constant
J
Zero
K
32-bit constant with the low 12 bits clear (a constant that can be
loaded with the sethi instruction)
L
A constant in the range supported by movcc instructions
M
A constant in the range supported by movrcc instructions
N
Same as K, except that it verifies that bits that are not in the
lower 32-bit range are all zero. Must be used instead of K for
modes wider than SImode
O
The constant 4096
G
Floating-point zero
H
Signed 13-bit constant, sign-extended to 32 or 64 bits
Q
Floating-point constant whose integral representation can
be moved into an integer register using a single sethi
instruction
R
Floating-point constant whose integral representation can
be moved into an integer register using a single mov
instruction
S
Floating-point constant whose integral representation can
be moved into an integer register using a high/lo_sum
instruction sequence
T
Memory address aligned to an 8-byte boundary
U
Even register
W
Memory address for e constraint registers.
TMS320C3x/C4x--c4x.h
a
Auxiliary (address) register (ar0-ar7)
b
Stack pointer register (sp)
c
Standard (32-bit) precision integer register
f
Extended (40-bit) precision register (r0-r11)
k
Block count register (bk)
q
Extended (40-bit) precision low register (r0-r7)
t
Extended (40-bit) precision register (r0-r1)
u
Extended (40-bit) precision register (r2-r3)
v
Repeat count register (rc)
x
Index register (ir0-ir1)
y
Status (condition code) register (st)
z
Data page register (dp)
G
Floating-point zero
H
Immediate 16-bit floating-point constant
I
Signed 16-bit constant
J
Signed 8-bit constant
K
Signed 5-bit constant
L
Unsigned 16-bit constant
M
Unsigned 8-bit constant
N
Ones complement of unsigned 16-bit constant
O
High 16-bit constant (32-bit constant with 16 LSBs zero)
Q
Indirect memory reference with signed 8-bit or index register displacement
R
Indirect memory reference with unsigned 5-bit displacement
S
Indirect memory reference with 1 bit or index register displacement
