2.4 Variables Make Makefiles Simpler
In our example, we had to list all the object files twice in the rule for
`edit' (repeated here):
| edit : main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
cc -o edit main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
|
Such duplication is error-prone; if a new object file is added to the
system, we might add it to one list and forget the other. We can eliminate
the risk and simplify the makefile by using a variable. Variables
allow a text string to be defined once and substituted in multiple places
later (see section How to Use Variables).
It is standard practice for every makefile to have a variable named
objects
, OBJECTS
, objs
, OBJS
, obj
,
or OBJ
which is a list of all object file names. We would
define such a variable objects
with a line like this in the
makefile:
| objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
|
Then, each place we want to put a list of the object file names, we can
substitute the variable's value by writing `$(objects)'
(see section How to Use Variables).
Here is how the complete simple makefile looks when you use a variable
for the object files:
| objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
edit : $(objects)
cc -o edit $(objects)
main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h command.h
cc -c command.c
display.o : display.c defs.h buffer.h
cc -c display.c
insert.o : insert.c defs.h buffer.h
cc -c insert.c
search.o : search.c defs.h buffer.h
cc -c search.c
files.o : files.c defs.h buffer.h command.h
cc -c files.c
utils.o : utils.c defs.h
cc -c utils.c
clean :
rm edit $(objects)
|